wimax/wibro rf mxfe miso transceiver AD9355 rev. spa information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features rf transceiver with integrated adcs and dacs ieee 802.16 wimax/wibro dual receivers, single transmitter operating band: 3.3 ghz to 3.8 ghz 3.5 mhz < bw < 10 mhz superior receiver sensitivity with nf < 3.5 db manual rx gain or autonomous agc mode highly linear and spectrally pure transmitter tx evm = ?38 db tx noise floor < ?134 dbm/hz at f offset > 22 mhz tx power control range of 58 db, resolution of 0.25 db integrated fractional-n synthesizer 10 hz lo step size lo integrated phase noise < 0.5rms automatic frequency correction < 0.012 ppm industry-standard jesd-207 digital interface applications bwa/wimax/wibro cpes usb dongles/minicards pico and femto base stations proprietary radio systems general description the AD9355 is a radio frequency (rf) transceiver with a single transmitter and dual receivers fully integrated into the device. this allows the part to be used for mobile and fixed wimax/wibro wireless network systems. by incorporating an rf mxfe?, the AD9355 offers the combination of an rf front end and a mixed- signal baseband, enabling an easy-to-use jesd-207-compliant digital interface to the baseband application-specific integrated circuit (asic) or field-programmable gate array (fpga). in addition, the AD9355 operates in the 3.3 ghz to 3.8 ghz range, covering most of the licensed and unlicensed bands. channel bandwidths of 3.5 mhz, 4.375 mhz, 5 mhz, 7 mhz, 8.75 mhz, and 10 mhz are supported. the direct-conversion receivers have state-of-the-art noise figure (nf) and linearity and, with the exception of baluns, do not require external components. the complete rf subsystem integrates autonomous automatic gain control (agc) loops and dc offset corrections, thus eliminating the need for high speed interaction with the baseband processor. the received signal is digitized with a set of four analog-to-digital converters (adcs) with high dynamic range. decimation and functional block diagram adc adc dac ctrl AD9355 rx1_n, rx1_p 4 2 4 2 2 10 2 tx_n, tx_p pw_det radio switching* (gpo0 to gpo3) spi port txnrx d[9:0] data_clk dv/fb_clk refclk xtalp xtaln ctrl_out[1:0] auxadc auxdac gpo ldos lo synth data interface rx2_n, rx2_p adc dac dac adc adc filter filter filter *radio switching is one possible use for the gpo pins. 07633-001 figure 1. channel filters produce a 10-bit output signal at the appropriate sample rate determined by the bandwidth mode. the transmit path interpolates 10-bit input data before converting it to the analog domain, and then upconverting it to the carrier frequency. the highly linear transmit path has excellent spectral purity with sideband noise less than ?134 dbm/hz at 22 mhz offset, and it offers an error vector magnitude (evm) of ?38 db at 0 dbm output power. the transmit power is detected by an accurate power detector with a range of more than 40 db and 0.5 db steps. the output power can be calibrated at the factory by a single measurement. the reference frequency is produced by an internal digitally controlled crystal oscillator (dcxo) that has a programmable frequency offset correction with a resolution of 0.012 ppm, thus reducing the total bill of materials (bom) of the device. an internal auxiliary adc and an auxiliary digital-to-analog converter (dac) are available for system monitoring and control. four general-purpose i/os are also included and can be register programmed or automatically sequenced by a user- defined state machine. mode control is via a 3- or 4-wire serial port and four real-time i/o control pins. the AD9355 is powered either from a single 3.3 v supply or, for power savings, from dual supplies and contains on-chip low dropout (ldo) regulators. the AD9355 is packaged in an 8 mm 8 mm, 56-lead lead frame chip scale package (lfcsp).
AD9355 rev. spa | page 2 of 2 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07633f-0-4/09(spa)
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